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[arcilator] Failed to legalize 'sim.clocked_terminate' and dangling macro references

Status: Open.

#10087 In llvm/circt;

· nanjo712 opened on Mar 31, 2026

[Calyx Emitter] Avoid emitting redundant write_en = 0 to satisfy write_together for reads

Status: Open.

#10074 In llvm/circt;

· Abhilekhgautam opened on Mar 29, 2026

[FIRRTL] Enable access to IMDCE at smaller granularities

enhancementNew feature or requestNew feature or request

FIRRTLInvolving the `firrtl` dialectInvolving the `firrtl` dialect

ReducerRelated to `circt-reduce`Related to `circt-reduce`

Status: Open.

#10055 In llvm/circt;

· seldridge opened on Mar 26, 2026

[FSM][CalyxToFSM] Should fsm.machine be IsolatedFromAbove?

Status: Open.

#10045 In llvm/circt;

· TaoBi22 opened on Mar 26, 2026

[FIRRTL] Improve Error Messages in InferDomains

FIRRTLInvolving the `firrtl` dialectInvolving the `firrtl` dialect

Status: Open.

#10041 In llvm/circt;

· seldridge opened on Mar 26, 2026

[SCF to Calyx] Generates external memory outside top level component

Status: Open.

#10036 In llvm/circt;

· Abhilekhgautam opened on Mar 25, 2026

FIRRTL not giving sink name

Status: Open.

#10031 In llvm/circt;

· mm-s-gautham opened on Mar 25, 2026

HWMemSimImplPass crashes with SIGFPE on zero-width memory when -disable-opt is used

Status: Open.

#9998 In llvm/circt;

· benreynwar opened on Mar 21, 2026

[circt-verilog] Add support for Slang -f and -F flags

ImportVerilog

Verilog/SystemVerilogInvolving a Verilog dialectInvolving a Verilog dialect

Status: Open.

#9987 In llvm/circt;

· satnam6502 opened on Mar 20, 2026

[ExportVerilog] Invalid XMR path for inner symbols defined in generate case op.

Status: Open.

#9972 In llvm/circt;

· uenoku opened on Mar 18, 2026

ImportVerilog may be non-deterministic

ImportVerilog

Status: Open.

#9971 In llvm/circt;

· fabianschuiki opened on Mar 18, 2026

[circt-verilog] Need to carry macro defined in previous file?

Status: Open.

#9963 In llvm/circt;

· uenoku opened on Mar 17, 2026